在ARMv8-a構(gòu)架中，設(shè)計的分層意識越來越明顯了。不同的中斷等級分為4層，由EL0-EL3。各自不同的層級承擔(dān)著不同層級的權(quán)限以及設(shè)計目的。具體的內(nèi)容還在學(xué)，剛開始理解得可能還是十分粗淺，知道的信息還并不全面，但慢慢地收集信息就成了一定的規(guī)模，主要還是在參考構(gòu)架手冊的內(nèi)容。主要還是先當(dāng)作草稿來看待，先定個大概的構(gòu)型先，等見識多了有不同的看法的時候再重新做出評價與刪改。

#define EL0 lowest Exception Level

#define EL1 privileged exception level

#define EL2 hypervision exception level

#define EL3 secure monitor exception level

#define usage_el0 user app

#define usage_el1 operating system

#define usage_el2 hypervision for non-secure code

#define usage_el3 secure grautee

#define HVC Hypervision Call

{

由TRAP解析,抓取低EL發(fā)出的指令到Hypervision中執(zhí)行,以MRC指令讀取系統(tǒng)寄存器為例子:

TRAP MRC PMCR為例：

.P7417(指令與協(xié)處理器)

MRC固定要用參數(shù)表：(MRC是指從General-purpose寫值到System register)

coproc(協(xié)處理器) opc1 CRn CRm opc2

0b1111 0b000 0b1001 0b1100 0b000

這套參數(shù)編碼對應(yīng)于PMCR的名字以及System instruction encoding space:

{coproc(協(xié)處理器) opc1 CRn CRm opc2}

此時 COPROC[0]==1-->P15作為encoding space

而ARM構(gòu)架中可以由CP15協(xié)處理器來控制cache\TCM和存儲器管理,協(xié)處理器還可以用于指令擴展.

CP15是system control coprocessor專門協(xié)助處理MCR\MRC提供的具體寄存器(系統(tǒng)級)配置和控制CACHE\MMU\保護\等

其有16個32位寄存器作為內(nèi)容,分別在用于標志指令狀態(tài)位,執(zhí)行指令執(zhí)行控制(包括執(zhí)行模式eg.cash\noncash protect\nonprotect等)

(現(xiàn)在找到的Trap Control在這里一定有它在這里的擴展,影響協(xié)處理器擴展在nosecure狀態(tài)下轉(zhuǎn)換EL執(zhí)行的指令模式)

.Page 5395 TRAP EC VALUE

ESR_ELx value holds syndrome information for an exception taken to ELx:

ESR_ELx.EC Exception Class give imformation about 1.the casuse of the exception, 2. the encoding of the associated ISS

對于Trapped MCR/MRC 使用P15,EC=0x4對應(yīng)于由低EL通過Trap抓取轉(zhuǎn)跳到高EL執(zhí)行的指令處理模式

.Page 9331

對于另一個例子MRC MPIDR,觀察它在低EL下的行為:

EL1:

1.受當(dāng)EL2Enabeld時:HSTR_EL2.TO,HSTR.T0決定了Trap的行為是否啟動來按EL2執(zhí)行指令

2.其他高EL情形下,直接讀寫

EL0:UNDEFINED EL0:UNDEFINED

.P9676 PMCR

在這里一些TRAP控制的確也在控制著TRAP的對協(xié)處理器解析指令的一部分影響

}

#define SMC Secure Monitor Call

{

/* .Page7587

* 除了TRAP的要素解析針對低EL層級做轉(zhuǎn)換到高層級的指令,還有一種指令也是能跨越EL的局限。

* SMC.指令(協(xié)處理器/主處理器)的解析由在SCR_EL3的第7位控制是否工作.其原文是這樣說的:

SMD, bit [7]

Secure Monitor Call disable. Disables SMC instructions at EL1 and above, from any Security state

and both Execution states, reported using an ESR_ELx.EC value of 0x00.

0b0 SMC instructions are enabled at EL3, EL2 and EL1.

0b1 SMC instructions are UNDEFINED

就其作用效果,該指令是能產(chǎn)生一個安全控制器的呼叫中斷,但只在EL1或更高的EL等級下有效.無權(quán)限的軟件只能走操作

系統(tǒng)規(guī)定的流程步驟操作,或者由另一部分執(zhí)行在EL或更高EL的軟件輔助.原文這樣說:

The SMC instruction causes a Secure Monitor Call exception, but only if software execution is

at EL1 or higher. Unprivileged software can only cause a Secure Monitor Call exception by

methods defined by the operating system, or by another component of the software system

that executes at EL1 or higher

具體來說,轉(zhuǎn)跳到怎樣一個EL中斷的安全等級是由寄存器控制的:

SCR.SCD HCR.TSC SEQ

0 0 EL3

\ 1 EL2 (相當(dāng)與變成了Hypervision Call了)

else else UNDEFIEND or UNPREDICTABLE

而轉(zhuǎn)跳到該EL等級下的中斷所執(zhí)行的指令操作可以緊跟一個0-15的編號分配,如"smc 7",雖然ARM并不推薦這樣做

<imm4> Is a 4-bit unsigned immediate value, in the range 0 to 15, encoded in the "imm4" field. This is

ignored by the PE. The Secure Monitor Call exception handler (Secure Monitor code) can use this

value to determine what service is being requested, but Arm does not recommend this.

對于這樣一個能夠把一個線程的執(zhí)行模擬/修飾位另一個線程的執(zhí)行而不必需要數(shù)據(jù)(身份信息等.)同步匹配的指令,

構(gòu)架采取一定的限制措施：

并發(fā)修改并執(zhí)行指令可以達到采用非并發(fā)執(zhí)行地等效執(zhí)行結(jié)果,在同一個EL執(zhí)行等級內(nèi).而對于SMC指令它是被這種并

發(fā)執(zhí)行模式排除在外的指令.參考原文于:

The architecture limits the set of instructions that can be executed by one thread of execution as they are being

modified by another thread of execution without requiring explicit synchronization.

Concurrent modification and execution of instructions can lead to the resulting instruction performing any behavior

that can be achieved by executing any sequence of instructions that can be executed from the same Exception level,

except where the instruction before modification and the instruction after modification are:

? When executing the A32 instruction set, a B, BKPT, BL, HVC, ISB, NOP, SMC, or SVC instruction.

? When executing the T32 instruction set. a 16-bit B, BKPT, BLX, BX, NOP, or SVC instruction.

*/