? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 產(chǎn)品詳情資料：

注：有關(guān)供應(yīng)商提供的芯片和其他第三方電路板組件的更多信息，請參閱相關(guān)文檔附錄中標(biāo)題為“適用的非摩托羅拉文檔”的部分。下圖（表1-7）中所指的DRAM均為奇偶保護(hù)型DRAM，與MVME162LX 200/300系列中的許多電路板一起提供。本指南的MCchip一章介紹了此映射所概述的芯片寄存器。對于帶有ECC保護(hù)DRAM的電路板，請參閱下表1-10和本指南的MCECC芯片章節(jié)。注意：MVME162LX 200/300系列上的IPIC芯片***多支持四個工業(yè)封裝（IP）接口，***為IP_a到IP_d。200/300系列本身可容納兩個IP：IP_a和IP_b。在以下映射中，適用于IP_c和IP_d的段未在MVME162LX 200/300系列中使用。IPIC控制和狀態(tài)寄存器（CSR）匯總?cè)绫?-9所示。CSR可以以字節(jié)、單詞或長單詞的形式訪問。它們不應(yīng)作為行訪問。表中以字節(jié)表示。注意：下表（表1-10）中所指的DRAM均為ECC保護(hù)型DRAM，即MVME162LX 200/300系列中大多數(shù)主板所提供的DRAM類型。本指南的MCECC一章介紹了此映射所概述的芯片寄存器。對于具有奇偶校驗保護(hù)DRAM的電路板，請參見上文表1-7和本指南的MCchip一章。

? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ???產(chǎn)品英文詳情料:

Note For further information on the vendor-supplied chips and other third-party board components, see the section entitled “Applicable Non-Motorola Documentation” in the Related Documentation Appendix.The DRAM referred to in the following map (Table 1-7) is all parity-protected, the type of DRAM supplied with many of the boards in the MVME162LX 200/300 Series. The chip registers outlined by this map are covered in the MCchip chapter of this Guide. For the boards with ECC-protected DRAM see below, Table 1-10, and the MCECC chip chapter of this Guide.Note The IPIC chip on the MVME162LX 200/300 Series supports up to four IndustryPack (IP) interfaces, designated IP_a through IP_d. The 200/300 Series itself accommodates two IPs: IP_a and IP_b. In the maps that follow, the segments applicable to IP_c and IP_d are not used in the MVME162LX 200/300 Series.A summary of the IPIC Control and Status Registers (CSRs) is shown in Table 1-9. The CSRs can be accessed as bytes, words, or longwords. They should not be accessed as lines. They are shown in the table as bytes.Note The DRAM referred to in the following map (Table 1-10) is all ECC-protected, the type of DRAM supplied with most of the boards in the MVME162LX 200/300 Series. The chip registers outlined by this map are covered in the MCECC chapter of this Guide. For the boards with parity-protected DRAM see above, Table 1-7, and the MCchip chapter of this Guide.