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半導(dǎo)體芯片，人類文明史上最耀眼的智慧結(jié)晶之一

Semiconductor chip, one of the most dazzling wisdom crystals of all the time

其設(shè)計與制造之精巧，讓人類自己都驚嘆不已

Even human are amazed of its designing and making compactness

但它說到底也要從最基礎(chǔ)的結(jié)構(gòu)——晶體管出發(fā)

But it’s based on the basic structure, transistor

你好

Hello

這里是一個成功忘拿了麥克風(fēng)不得不拿手機(jī)錄音的屑up

This is an unlucky up who succeeded to forget to get his microphone

今天我們看一看，在芯片工藝提升的道路上，人類做了哪些創(chuàng)新

Today, let’s talk about what creations made by human in chip craft development

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芯片工藝的提升，主要就是晶體管工藝制程的壓縮

Chip craft’s improvement mainly depends on compressing to transistor craft process

還記得中學(xué)物理課本上的這張圖嗎

Did you still remember this picture in middle school physical textbook?

在鐵片上施加電壓，按照電阻定律R=ρL/S

Apply voltage to the iron sheet, according to R=ρL/S

只要同步裁剪長度和橫截面積就能做到電阻不變，相等電壓下電流也不變

Current equals the past in the same voltage as long as you change its length and Cross-sectional area synchronously

只是散熱面積減小

Merely the heat dissipation area decreases

所以在集成電路發(fā)展的早期，人們主要面對的是功耗而非玄學(xué)問題

So in early time of IC development, the main problem is power consumption, not metaphysical

但現(xiàn)在我們確實在面臨玄學(xué)問題

But we need to face it now

究竟怎么個玄法，就要從半導(dǎo)體本身出發(fā)

Let’s discuss it from semiconductor itself

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單晶硅和金剛石的結(jié)構(gòu)一樣都是對稱的四根共價鍵連著

Signal crystal Si has the same structure as diamond, with 4 symmetrical sharing bonds

在這樣的本征半導(dǎo)體中摻雜第三主族元素（例如B）會缺少一個電子形成空穴，曰P型半導(dǎo)體

Doped the 3rd main group element(eg : B) in intrinsic semiconductors, and you will lose a electron and get a cavity. This is P-type semiconductor.

摻雜第五主族元素（例如P）會有多余的自由電子，曰N型半導(dǎo)體

Doped 5th main group element(eg : P) and you will get another free electron. This is N-type semiconductor

二者挨著時空穴與自由電子之間會形成一個內(nèi)部電場

When P and N type next to each other, cavities and free electrons will make an internal electric field

當(dāng)外界施加正向電壓時內(nèi)部電場推著電子走，反向電壓時擋著電子走，電阻不一樣

When you apply forward volt it will push electrons and stop when the reverse volt, so it has different resistances

這就是二極管內(nèi)PN結(jié)的單向?qū)щ娦?/p>

Which is called unidirectional conductivity of the PN junction inside the diode

而三極管有發(fā)射極、集電極和基極三個電極

The 3-electrode-transistor has emitter, collector and base

以NPN的為例，當(dāng)與P區(qū)相連的基極吸收少量來自發(fā)射極的自由電子時

For an example as NPN type, when the base next to P field absorbs few free electrons from the emitter

集電極會吸收大部分，從而放大輸入的電流或電壓信號，甚至實現(xiàn)控制開關(guān)的作用

The collector will absorb the most, so that it can zoom inputting current or volt signals, even become a switch

但后來科學(xué)家們發(fā)明了金屬氧化物半導(dǎo)體場效應(yīng)管（MOSFET）

But scientists invented MOSFET

它有源極、漏極、柵極和襯底四部分

It has Source, drain, gate, and substrate

還是以NPN的為例，源極和漏極都連著N型半導(dǎo)體，內(nèi)含大量自由電子

For NPN type, the source and drain connect to N-type semiconductor with many free electron

而柵極在兩方之間，用二氧化硅隔開

The gate is between them and is separated by SiO2

當(dāng)我們在柵極與襯底之間施加一定的正向電壓時

When we apply volt from the gate to the substrate

會有大量電子被吸過來在源極和漏極形成N溝道，從而導(dǎo)電

Many electrons will be absorbed there to form a N-channel and conductive

通過對柵極電勢的修改實現(xiàn)壓控電阻和控制開關(guān)

You can implement a volt-control resistance or a switch

由于二氧化硅絕緣使得MOSFET的輸入電流與功率為0，降低了功耗，從而壓縮了芯片的工藝制程

Insulating SiO2 leads inputting current and power to 0, reduces power consumption, and compresses the process

但是這有個前提是柵極不向漏極漏電

However, you need to be sure that the gate won’t creepage to the drain

很不幸，現(xiàn)在有個玄學(xué)問題擺在你面前——量子遂穿

Unluckily, now there is a metaphysical problem. quantum penetration

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按照德布羅意的物質(zhì)波觀點，電子也有波粒二象性

According to De Broglie’s matter wave view, electron also has wave-particle duality

電子的軌道就是駐波存在的結(jié)果

Orbits are a result of standing waves

于是科學(xué)家們提出波函數(shù)的概念

So scientists point out wave function

它表示某處某時出現(xiàn)概率（或概率密度）的相對大小，正比于波的能量

It represents the relative magnitude of the probability (or probability density) of occurrence at a certain time, proportional to the energy of the wave

一個地方的波函數(shù)值越大，粒子在這里出現(xiàn)的可能性也就越大

The large wave function value in a place, the more possible a particle appears there

以一維坐標(biāo)系為例，設(shè)電子的動量與約化普朗克常數(shù)之比為k

In 1D coordinate system, let k=p/hbar

結(jié)合能量量子化 以及動量與動能的關(guān)系

As you know ?and

可得 ????????????than you find

代入波動方程~后得波函數(shù)ψ=~

Put them into wave equation and get the wave function psi=~

接著對x和t分別求二階和一階導(dǎo)數(shù)，獲取動量與能量算子

Then find the second and first derivatives for x and t, respectively, to obtain the momentum and energy operators

設(shè)電子一開始具備E的動能且勢能為0

Let an electron has moving energy E and potential energy 0

現(xiàn)在，在電子前面有一個勢壘，爬上去就會有U的勢能

In front of it exists a barrier with potential energy U

你會理所當(dāng)然地認(rèn)為只E>U時電子才有足夠的能量越過去

You must say, the electron will fly over it only when E>U

這就和撐桿跳時要積攢彈性勢能才能跳過去沒有什么區(qū)別

just like accumulating elastic potential energy to jump through a pole vault

但實際上，當(dāng)E<U時，k和p的值依然存在，只不過是虛數(shù)

Instead, when E<U, k and p are still exist, although they are image numbers

此時經(jīng)過一系列數(shù)學(xué)變換，有~

At this time, after a series of mathematical transformations, there is ~

波函數(shù)的二階可導(dǎo)意味著它一定是自身和一階連續(xù)的

Wave function is 2nd derivable means it and its 1st derivative are continuous

利用勢壘的邊界條件得出，當(dāng)取勢壘左邊的x時波函數(shù)大于0

Use barrier’s boundary condition to find that ψ>0 when x is left

這很好理解，是電子被勢壘反彈回來了

It’s easy to understand because the electron is bounced back by the barrier

但是取勢壘右邊的x時波函數(shù)依舊大于0，也就是說，電子有一定的概率出現(xiàn)在右邊

But ψ>0 even x is right, other words, electrons have some possibility to appear in the right

這就是量子遂穿，也叫勢壘貫穿

That’s quantum penetration, also called barrier penetration

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為了讓柵極和漏極之間電流足夠小，有較強(qiáng)的控制力

To reduce the current between the gate and the drain so as to get strong control

柵極和溝道之間必須有足夠大的接觸面積

The gate must have large enough exposure area with the channel

傳統(tǒng)的工藝只是讓柵極和氧化層平鋪在上面

Traditional process paves gates and dioxide on chips

但隨著晶體管越來越小，柵極寬度已經(jīng)小到無法讓平鋪的工藝解決漏電難題

But with the shrinking of transistors, gate width is to small to face this problem

所以22nm以后，人們將過去挖坑式的源極和漏極立了起來

So after 22nm, someone The source erects gates and drains of the previous digging type

柵極和氧化層繞著源極和漏極，形成一個魚鰭式的結(jié)構(gòu)

The source and drain are surrounded by the gate and dioxide and form a structure like fin

三面環(huán)繞使得接觸面積大大增加，這就是鰭式晶體管（FinFET）

3 sides surrounding enlarges the exposure area, that is FinFET

那既然三面環(huán)繞，可不可以再徹底一點，四面環(huán)繞呢？

So, why not change 3 sides to 4 sides?

這時，我們需要把源極和漏極完全拉上來

Now we need to pull the source and drain up completely

讓柵極完全圍住中間的部分，這樣三面變成了四面，更好控制

Let the gate surround the middle part and turn 3 sides to 4 sides, easier to control

而且，如果我們將柵極的高度提起，在其中插入多條摻雜的半導(dǎo)體

What’s more, if we enlarge the height of gate and put more doped semiconductor

就能用一個大柵極去同時控制多個棒狀的結(jié)構(gòu)

We can control more stakes with one gate

一端作為源極，另一端作為漏極

A side is the source and the other is the drain

也就是說，將這兩個電極各自分割為多個不同的部分，每個部分都單獨環(huán)繞

That’s mean we divide the 2 electrodes into many parts and each part is surrounded individually

現(xiàn)在柵極的控制深入到了溝道內(nèi)部，就能實現(xiàn)更多面環(huán)繞

Than the control of the gate goes deep inside the channel and implement more sides surrounding

這就是全環(huán)繞式晶體管（GAA）

This is GAA

除了這兩種增大接觸面積的防漏電方式

Expect these 2 ways to enlarge exposure area to stop creepage

還有改造材料的high-k和low-k方案

There are high-k and low-k ways, too

早期柵極的材料也是采用絕緣的二氧化硅

Early material of gates is insulating SiO2

你一定會問為什么不能把二氧化硅做得厚一點，這樣不就不容易漏電了嗎

You must ask why not make SiO2 more thick to stop creepage

實際上，一方面現(xiàn)在的晶體管結(jié)構(gòu)都是立體的，要縮減工藝制程就最好讓它薄一些

In fact, on the an hand transistors is 3D now. It’s batter to make it more thin.

另一方面加厚會導(dǎo)致柵極的電容降低

On the other hand thick SiO2 reduces the capacitance of the gate

當(dāng)你需要晶體管導(dǎo)通時同樣輸入電壓下能吸過來的電荷會減少

The charge you absorb you be down in the same inputting volt when you need the transistor to conduct

抑制溝道擴(kuò)充，不利于導(dǎo)通

This will restrain the channel from expanding and is bad for conduction

所以人們企圖采用介電常數(shù)較大的材料（例如 ）取代二氧化硅

So someone wants to use material with high dielectric constant(eg: ) to take the place of SiO2

這樣在相同厚度下的柵極電容更大，有利于導(dǎo)通還方便柵極和氧化層的變薄

In this way the gate capacitance is larger than before in the equal thickness, which is beneficial to make gates and dioxide layer thinner

進(jìn)一步縮減了工藝制程，曰high-k方案

?

reducing the process process, and this is high-k solution

但是要提升半導(dǎo)體芯片的工藝，除了晶體管要縮減外，另一個東西也不容忽視

But you must also focus on another problem expect reducing your transistors

那就是導(dǎo)線

That’s conducting wires.

本來我們的導(dǎo)線一般都是長度遠(yuǎn)大于橫截面上的直徑的

Generally speaking, our wires lengths are much more than the diameters of their cross sections

很多時候?qū)Ь€的電容和電感根本懶得去管

You must be too lazy to focus on the capacitances and inductances of wires in many cases

但是在芯片中長度和橫截面上的直徑可以不相差那么大

But the gap may be less in chips

所以不僅僅是導(dǎo)線的電阻，其電容和電感都是嚴(yán)重的干擾項

So the resistances, even capacitances and inductances are serious distractors

于是為了降低計算難度，導(dǎo)線需要使用介電常數(shù)低的材料

In these cases we need to use low dielectric constant material to down the calculating difficulties

那就是low-k方案

That’s low-k solution

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原本溝道的形成，我們是通過控制柵極和襯底之間電壓來實現(xiàn)的

Originally the form of channels is implemented by the control between the gate and substrate

而漏電的困境在于量子遂穿

The dilemma of creepage is because of?quantum penetration

但是也有人反其道而行之，將量子遂穿設(shè)成了不同軌道的遂穿

However, someone does the opposite thing, set the quantum penetration as the penetration between different orbits

我們知道原子與原子之間形成化學(xué)鍵時原子軌道會有能量的升高與降低

We know the atom orbits energy will up or down when chemical bonds shape along the atoms

能量高的形成了導(dǎo)帶，能量低的形成了價帶

High energy orbits become conduction bands while the low become valence bands

中間夾雜著一條禁帶

And an energy gap is between them

如果不是外界電場的暴力功能，而是利用遂穿讓電子或空穴穿越兩帶

If you make electrons travel in these 2 bands with penetration instead of extern electronic field

實現(xiàn)新的控制，這就能大大提高晶體管的工作性能

in order to make new control, this will improve transistors’ working performance

greatly

此類思路制成的叫做隧穿場效應(yīng)晶體管

This is tunneling field effect transistors

?

?

只是，柵極的寬度，真的需要那么小嗎？集成度的提高有必要死磕這單獨一個問題嗎？

However, do you really need to make gate widths so small? Is it indispensable?

并不是

No

當(dāng)我們把目光向上揚起，讓躺平的溝道垂直于晶圓本身而堅挺中柵極中央

When we raise our gaze and lift the laying channel up, perpendicular to the wafer plane

就能在另一個維度上任意擴(kuò)展柵極寬度與接觸面積

You can expand the gate width and exposure area arbitrarily

神奇的垂直傳輸納米片場效應(yīng)晶體管（VTFET）誕生了

This is VTFET

那既然GAA里面源極和柵極可以分成多個半導(dǎo)體棍子而被深入包圍

Since the source and draft can be divided into semiconductor stakes and be surrounded deep

我是不是也可以做得更離譜點，在一個狹窄的地基上建起智慧的高塔

I can also do more outrageously, build a wisdom tower on a narrow base

沒錯，這就是3D堆疊技術(shù)

Yes, what I mean is 3D stacking

繞開傳統(tǒng)的柵極寬度要求，實現(xiàn)同樣光刻工藝下更高的集成度

Bypassing traditional gate width requirements to achieve a higher level of integration in the same lithography process

比如，將過去FinFET和GAA的晶體管一個一個相互垂直地擺在一起

For example, place transistors of FinFET or GAA in the past vertically mutually

用一個柱子或是坑道相連，P型和N型半導(dǎo)體交替登場，這就是互補(bǔ)場效應(yīng)晶體管（CFET）

connect with pillars or tunnels, PandN-type semiconductor appear alternately, and you will get CFET

2022年7月15日，中科院微電子研究所在這方面取得重大突破

On July 15, 2022, the Institute of Microelectronics of the Chinese Academy of Sciences made a major breakthrough in this regard

利用SiNx與SiO2 進(jìn)行分步溝道形貌刻蝕（反正我看不懂）

SiNx and SiO2 were used for step-by-step channel morphology etching(I can’t understand what it is)

實現(xiàn)了混合通道互補(bǔ)場效應(yīng)管（HF-CFET）

Implementing HF-CFET

?

?

在一些存儲器例如NAND芯片上，人們大量使用以電子多少表示二進(jìn)制的浮柵晶體管

In some savers such as NAND chips, people use quantity of electrons in float gate transistors to indicate binary numbers

一個個柵極圍繞著溝道，而溝道則是以造柱子或挖深坑的方式實現(xiàn)

Gates surround channels and channels are made by building pillars and digging pits

但存儲器內(nèi)部可不是只有一大堆觸發(fā)器在那里保存信息

But there are not only massive latches

還必須有譯碼等電路負(fù)責(zé)尋址等其它工作，這些電路如果和浮柵晶體管分開

There are also decoders and others to be responsible for addressing etc., if they are separated from float gate transistors

就會單獨占據(jù)一塊晶圓面積

They will take a single place

所以科學(xué)家們發(fā)明了階梯式的存儲電路，浮柵晶體管一層一層階梯狀排開

So scientists invented stepped saving circuits. Float gate transistors are arrayed floor by floor.

導(dǎo)線則是豎著與之階梯狀相連

Wires are connected to them step by step

也有人把控制電路擺在存儲電路底部或分層地嵌入其中

There are also some people lay controlling circuits bottom or inside saving parts

但這樣對于制作工藝，尤其是刻蝕環(huán)節(jié)的要求太高

But this process has a heigh requirement for etching

這時，中國的長江存儲，就是那個搞出恐怖的232層的長江存儲

Now, Yangtze River storage of China, yes, who made a 232-floors NAND chips

進(jìn)行了一種奇葩的操作

does a wonderful operation

他們將存儲電路和控制電路分開生產(chǎn)做成兩塊芯片

They produce saving and controlling circuits separately, making two chips

然后翻過來拼在一塊兒，合二為一，這就是現(xiàn)在的一點小小的中國震撼——Xtacking

Then they turn these thing over and stick together, which can be thought as a little Chinese shock，Xtacking

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?

說了這么多，相信你已經(jīng)理解了為什么說芯片工藝的提升

By above words, I hope you have understood why improvements of chip process

不僅僅是對科學(xué)家發(fā)量的挑戰(zhàn)，更是對一個國家工業(yè)體系的考驗

is not only a challenge for hair inventory, more a test for a country industry system

面對政治博弈下量子遂穿的玄學(xué)難題與各種科學(xué)的高山

In the face of the metaphysical puzzle of quantum penetration in political games and variate heigh mountains of science

有人選擇加大初動能，化作雄鷹翱翔而越；有人選擇修改波函數(shù)，化作長波衍射而穿

Someone decides to enlarge initial moving energy, flying over it as an eagle,

While other people decide to change the wave function, transcending the barrier as a long wave

有人選擇居高臨下降維打擊，有人選擇單挑神明升維打擊

Somebody will do dimension-down frighting from the heigh to the low, while some people will single gods out with dimension-up frighting

正視差距，不要怕，面對敵人不要跪，要狠狠地打

Face to the gap, but don’t be afraid. Facing the emery, don’t kneel. Instead, hit it with your force

相信自己，同志們，我們，能贏的

Believe yourself, comrades, we will win