verilog 中數(shù)組的詳細(xì)介紹
2023-07-05 10:22 作者:吃不消數(shù)電題 | 我要投稿
module TEST_CNT_ARRAY(
input wire clk,
input wire rst_n,
output wire[3:0] led_out
);
reg[31:0] men_cnt[1:64];
genvar i;
generate for(i=1;i<=64;i=i+1) begin : TEST_CNT
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
men_cnt[i] <= 32'd0;
else if(men_cnt[i] == 'd )
men_cnt[i] <= 32'd0;
else
men_cnt[i] <= men_cnt[i] + 1;
end?
end?
endgenerate
always@(posedge clk or negedge rst_n)
begin
if(~rst_n)
led_out <= 4'd1;
else if(men_cnt[i] == 'd)
led_out <= ~led_out;
else
led_out <= led_out;
end?
endmodule
標(biāo)簽：
