最近在各個(gè)平臺(tái)都看到了朱佳迪攻克1nm的新聞

而在新聞底下

又是無盡的嘲諷

那么，這個(gè)事兒是真的嗎？

百度找了一圈不管是文字 還是視頻的

都是一張圖

按圖搜圖找到的都是這個(gè)

最后，好不容易看到一個(gè)稿子，里面有文字截圖

有了文字就更好搜索了

于是，終于找到了這個(gè)新聞的源頭完整版截圖如下

Emerging AI applications, like chatbots that generate natural human language, demand denser, more powerful computer chips. But semiconductor chips are traditionally made with bulk materials, which are boxy 3D structures, so stacking multiple layers of transistors to create denser integrations is very difficult.

However, semiconductor transistors made from ultrathin 2D materials, each only about three atoms in thickness, could be stacked up to create more powerful chips. To this end, MIT researchers have now demonstrated a novel technology that can effectively and efficiently “grow” layers of 2D transition metal dichalcogenide (TMD) materials directly on top of a fully fabricated silicon chip to enable denser integrations.

Growing 2D materials directly onto a silicon CMOS wafer has posed a major challenge because the process usually requires temperatures of about 600 degrees Celsius, while silicon transistors and circuits could break down when heated above 400 degrees. Now, the interdisciplinary team of MIT researchers has developed a low-temperature growth process that does not damage the chip. The technology allows 2D semiconductor transistors to be directly integrated on top of standard silicon circuits.

In the past, researchers have grown 2D materials elsewhere and then transferred them onto a chip or a wafer. This often causes imperfections that hamper the performance of the final devices and circuits. Also, transferring the material smoothly becomes extremely difficult at wafer-scale. By contrast, this new process grows a smooth, highly uniform layer across an entire 8-inch wafer.

The new technology is also able to significantly reduce the time it takes to grow these materials. While previous approaches required more than a day to grow a single layer of 2D materials, the new approach can grow a uniform layer of TMD material in less than an hour over entire 8-inch wafers.

Due to its rapid speed and high uniformity, the new technology enabled the researchers to successfully integrate a 2D material layer onto much larger surfaces than has been previously demonstrated. This makes their method better-suited for use in commercial applications, where wafers that are 8 inches or larger are key.

“Using 2D materials is a powerful way to increase the density of an integrated circuit. What we are doing is like constructing a multistory building. If you have only one floor, which is the conventional case, it won’t hold many people. But with more floors, the building will hold more people that can enable amazing new things. Thanks to the heterogenous integration we are working on, we have silicon as the first floor and then we can have many floors of 2D materials directly integrated on top,” says Jiadi Zhu, an electrical engineering and computer science graduate student and co-lead author of a?paper?on this new technique.

Zhu wrote the paper with co-lead-author Ji-Hoon Park, an MIT postdoc; corresponding authors Jing Kong, professor of electrical engineering and computer science (EECS) and a member of the Research Laboratory for Electronics; and Tomás Palacios, professor of EECS and director of the Microsystems Technology Laboratories (MTL); as well as others at MIT, MIT Lincoln Laboratory, Oak Ridge National Laboratory, and Ericsson Research. The paper appears today in?Nature Nanotechnology.

Slim materials with vast potential

The 2D material the researchers focused on, molybdenum disulfide, is flexible, transparent, and exhibits powerful electronic and photonic properties that make it ideal for a semiconductor transistor. It is composed of a one-atom layer of molybdenum sandwiched between two atoms of sulfide.

Growing thin films of molybdenum disulfide on a surface with good uniformity is often accomplished through a process known as?metal-organic chemical vapor deposition?(MOCVD). Molybdenum hexacarbonyl and diethylene sulfur, two organic chemical compounds that contain molybdenum and sulfur atoms, vaporize and are heated inside the reaction chamber, where they “decompose” into smaller molecules. Then they link up through chemical reactions to form chains of molybdenum disulfide on a surface.

But decomposing these molybdenum and sulfur compounds, which are known as precursors, requires temperatures above 550 degrees Celsius, while silicon circuits start to degrade when temperatures surpass 400 degrees.

So, the researchers started by thinking outside the box — they designed and built an entirely new furnace for the metal-organic chemical vapor deposition process.

The oven consists of two chambers, a low-temperature region in the front, where the silicon wafer is placed, and a high-temperature region in the back. Vaporized molybdenum and sulfur precursors are pumped into the furnace. The molybdenum stays in the low-temperature region, where the temperature is kept below 400 degrees Celsius — hot enough to decompose the molybdenum precursor but not so hot that it damages the silicon chip.

The sulfur precursor flows through into the high-temperature region, where it decomposes. Then it flows back into the low-temperature region, where the chemical reaction to grow molybdenum disulfide on the surface of the wafer occurs.

“You can think about decomposition like making black pepper — you have a whole peppercorn and you grind it into a powder form. So, we smash and grind the pepper in the high-temperature region, then the powder flows back into the low-temperature region,” Zhu explains.

Faster growth and better uniformity

One problem with this process is that silicon circuits typically have aluminum or copper as a top layer so the chip can be connected to a package or carrier before it is mounted onto a printed circuit board. But sulfur causes these metals to sulfurize, the same way some metals rust when exposed to oxygen, which destroys their conductivity. The researchers prevented sulfurization by first depositing a very thin layer of passivation material on top of the chip. Then later they could open the passivation layer to make connections.

They also placed the silicon wafer into the low-temperature region of the furnace vertically, rather than horizontally. By placing it vertically, neither end is too close to the high-temperature region, so no part of the wafer is damaged by the heat. Plus, the molybdenum and sulfur gas molecules swirl around as they bump into the vertical chip, rather than flowing over a horizontal surface. This circulation effect improves the growth of molybdenum disulfide and leads to better material uniformity.

In addition to yielding a more uniform layer, their method was also much faster than other MOCVD processes. They could grow a layer in less than an hour, while typically the MOCVD growth process takes at least an entire day.

Using the state-of-the-art?MIT.Nano?facilities, they were able to demonstrate high material uniformity and quality across an 8-inch silicon wafer, which is especially important for industrial applications where bigger wafers are needed.

“By shortening the growth time, the process is much more efficient and could be more easily integrated into industrial fabrications. Plus, this is a silicon-compatible low-temperature process, which can be useful to push 2D materials further into the semiconductor industry,” Zhu says.

In the future, the researchers want to fine-tune their technique and use it to grow many stacked layers of 2D transistors. In addition, they want to explore the use of the low-temperature growth process for flexible surfaces, like polymers, textiles, or even papers. This could enable the integration of semiconductors onto everyday objects like clothing or notebooks.

“This work made an important progress in the synthesis technology of monolayer molybdenum disulfide material,” says Han Wang, the Robert G. and Mary G. Lane Endowed Early Career Chair and Associate Professor of Electrical and Computer Engineering and Chemical Engineering and Materials Science at the University of Southern California, who was not involved with this research. “The new capability of low thermal budget growth on an 8-inch scale enables the back-end-of-line integration of this material with silicon CMOS technology and paves the way for its future electronics application.”

This work is partially funded by the MIT Institute for Soldier Nanotechnologies, the National Science Foundation Center for Integrated Quantum Materials, Ericsson, MITRE, the U.S. Army Research Office, and the U.S. Department of Energy. The project also benefitted from the support of TSMC University Shuttle.

chatGTP翻譯如下

新興的人工智能應(yīng)用，如生成自然人類語言的聊天機(jī)器人，需要更密集、更強(qiáng)大的計(jì)算機(jī)芯片。但傳統(tǒng)上，半導(dǎo)體芯片是由立方體3D結(jié)構(gòu)的塊材料制成的，因此堆疊多個(gè)層次的晶體管以創(chuàng)建更密集的集成是非常困難的。

然而，由超薄2D材料制成的半導(dǎo)體晶體管，每個(gè)只有大約三個(gè)原子厚度，可以堆疊起來創(chuàng)建更強(qiáng)大的芯片。為此，MIT的研究人員現(xiàn)已展示了一種新穎技術(shù)，可以有效地和高效地“生長(zhǎng)”多層二維過渡金屬二硫化物（TMD）材料直接在完全制造好的硅片上，以實(shí)現(xiàn)更密集的集成。

將2D材料直接生長(zhǎng)在硅CMOS晶圓上一直是一個(gè)巨大的挑戰(zhàn)，因?yàn)檫@個(gè)過程通常需要約600攝氏度的溫度，而硅晶體管和電路在加熱至400攝氏度以上時(shí)可能會(huì)損壞?，F(xiàn)在，MIT的跨學(xué)科研究團(tuán)隊(duì)開發(fā)了一種不會(huì)損壞芯片的低溫生長(zhǎng)過程。該技術(shù)可使2D半導(dǎo)體晶體管直接集成在標(biāo)準(zhǔn)硅電路上。

過去，研究人員在其他地方生長(zhǎng)2D材料，然后將它們轉(zhuǎn)移到芯片或晶圓上。這經(jīng)常會(huì)導(dǎo)致缺陷，從而影響最終設(shè)備和電路的性能。此外，在晶圓規(guī)模上平滑轉(zhuǎn)移材料變得極為困難。相比之下，這種新方法在整個(gè)8英寸晶圓上生長(zhǎng)出了一層光滑、高度均勻的材料。

新技術(shù)也能夠顯著縮短生長(zhǎng)這些材料所需的時(shí)間。雖然之前的方法需要一天以上才能生長(zhǎng)一層2D材料，但新方法可以在一個(gè)小時(shí)內(nèi)在整個(gè)8英寸晶圓上生長(zhǎng)出一層TMD材料的均勻?qū)印?/p>

由于其快速的速度和高度均勻，因此新技術(shù)使研究人員成功地將2D材料層集成到比先前曾經(jīng)展示過的更大的表面上。這使得他們的方法更適合商業(yè)應(yīng)用，其中8英寸或更大的晶圓至關(guān)重要。

電氣工程和計(jì)算機(jī)科學(xué)研究生和本研究新技術(shù)的共同作者之一朱佳迪表示：“使用2D材料是提高集成電路密度的有力方式。我們正在做的就像建造多層樓房。如果只有一個(gè)樓層，也就是傳統(tǒng)情況下，它不會(huì)容納很多人。但是有了更多的樓層，建筑物將容納更多的人，從而實(shí)現(xiàn)驚人的新事物。由于我們正在進(jìn)行異質(zhì)集成，因此硅是第一層，然后可以將許多層2D材料直接集成在其上?！?/p>

該論文的共同作者還包括本文的共同作者Park Ji-Hoon、電氣工程和計(jì)算機(jī)科學(xué)（EECS）教授、電子研究實(shí)驗(yàn)室的成員孔晶教授以及微系統(tǒng)技術(shù)實(shí)驗(yàn)

有自媒體讓國人反思，自然也有說他不是中國人的。

但，他的臉書上，確實(shí)寫著自己是江蘇南京人。

當(dāng)然，現(xiàn)在可能已經(jīng)不是了。

怎么說呢？

對(duì)世界來說，這是個(gè)好事兒。

但是用來說國內(nèi)學(xué)術(shù)環(huán)境不行也大可不必。

記得大頭鷹直播的時(shí)候，有個(gè)在海外的小姐姐也說了，

在外面也是一個(gè)鳥樣。

找到鏈接了的話，我再補(bǔ)上。