幾乎所有SCR都表現(xiàn)出一定程度的關(guān)斷增益。

在陽(yáng)極電流的正常值下，負(fù)柵極電流

不會(huì)對(duì)內(nèi)部反饋產(chǎn)生足夠的影響

設(shè)備的環(huán)路，從而導(dǎo)致

陽(yáng)極電流。然而，它確實(shí)在

低陽(yáng)極電流水平；它可以通過

使用它來修改某些設(shè)備參數(shù)。明確地

可以減少關(guān)斷時(shí)間，并且可以減少保持電流

增加。減少關(guān)閉時(shí)間并增加保持時(shí)間

電流在逆變器或

全波相位控制電路，其中電感為

目前

當(dāng)然，負(fù)柵極電流可能由

使用外部偏置電源。它也可能由

利用在傳導(dǎo)過程中

柵極相對(duì)于陰極是正的，并且提供

外部傳導(dǎo)路徑，如柵極到陰極

電阻器。所有ON半導(dǎo)體SCR，例外

敏感門器件，采用內(nèi)置

柵極-陰極分流，產(chǎn)生與

負(fù)柵極電流。特性的進(jìn)一步變化

可以通過使用外部分流器來產(chǎn)生。調(diào)車

不會(huì)產(chǎn)生與

負(fù)偏置，因?yàn)樨?fù)柵極電流，甚至

在外部短路的情況下，受到橫向短路的限制

基層的電阻。使用外部負(fù)極時(shí)

偏置電流必須受到限制，并且必須小心

避免將柵極驅(qū)動(dòng)到雪崩區(qū)域。

上未顯示負(fù)柵極電流的影響

設(shè)備規(guī)格表。圖3.13中的曲線

表示對(duì)多個(gè)SCR進(jìn)行的測(cè)量，以及

因此不應(yīng)被視為規(guī)格限制。他們

然而，確實(shí)顯示出了明確的趨勢(shì)。例如，所有

SCR顯示關(guān)閉時(shí)間改善了約

通過使用負(fù)偏置直到?jīng)]有

獲得了進(jìn)一步的顯著改善。這個(gè)

使用外部分流器增加保持電流

電阻器的范圍通常在5%和75%之間，

而在負(fù)偏差的情況下，改善的范圍

通常在打開閘門值的2?1/2到7倍之間。

請(qǐng)注意，保持電流曲線是標(biāo)準(zhǔn)化的

參考打開的門值。

Almost all SCR’s exhibit some degree of turn?off gain.

At normal values of anode current, negative gate current

will not have sufficient effect upon the internal feedback

loop of the device to cause any significant change in

anode current. However, it does have a marked effect at

low anode current levels; it can be put to advantage by

using it to modify certain device parameters. Specifically,

turn?off time may be reduced and hold current may be

increased. Reduction of turn?off time and increase of hold

current are useful in such circuits as inverters or in

full?wave phase control circuits in which inductance is

present.

Negative gate current may, of course, be produced by

use of an external bias supply. It may also be produced by

taking advantage of the fact that during conduction the

gate is positive with respect to the cathode and providing

an external conduction path such as a gate?to?cathode

resistor. All ON Semiconductor SCR’s, with the exception

of sensitive gate devices, are constructed with a built in

gate?to?cathode shunt, which produces the same effect as

negative gate current. Further change in characteristics

can be produced by use of an external shunt. Shunting

does not produce as much of a change in characteristics as

does negative bias, since the negative gate current, even

with an external short circuit, is limited by the lateral

resistance of the base layer. When using external negative

bias the current must be limited, and care must be taken to

avoid driving the gate into the avalanche region.

The effects of negative gate current are not shown on

the device specification sheets. The curves in Figure 3.13

represent measurements made on a number of SCRs, and

should therefore not be considered as spec limits. They

do, however, show definite trends. For example, all of the

SCRs showed an improvement in turn?off time of about

one?third by using negative bias up to the point where no

further significant improvement was obtained. The

increase in hold current by use of an external shunt

resistor ranged typically between 5 and 75 percent,

whereas with negative bias, the range of improvement ran

typically between 2?1/2 and 7 times the open gate value.

Note that the holding current curves are normalized and are

referred to the open gate value.